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Design of all-optical logic gate based on two-dimensional photonic crystal

WU Rong ZHANG Hao-chen YANG Jian-ye

吴蓉, 张皓辰, 杨建业. 基于二维光子晶体全光逻辑门的设计[J]. 中国光学(中英文), 2024, 17(1): 245-251. doi: 10.37188/CO.EN-2023-0014
引用本文: 吴蓉, 张皓辰, 杨建业. 基于二维光子晶体全光逻辑门的设计[J]. 中国光学(中英文), 2024, 17(1): 245-251. doi: 10.37188/CO.EN-2023-0014
WU Rong, ZHANG Hao-chen, YANG Jian-ye. Design of all-optical logic gate based on two-dimensional photonic crystal[J]. Chinese Optics, 2024, 17(1): 245-251. doi: 10.37188/CO.EN-2023-0014
Citation: WU Rong, ZHANG Hao-chen, YANG Jian-ye. Design of all-optical logic gate based on two-dimensional photonic crystal[J]. Chinese Optics, 2024, 17(1): 245-251. doi: 10.37188/CO.EN-2023-0014

基于二维光子晶体全光逻辑门的设计

详细信息
  • 中图分类号: TN256

Design of all-optical logic gate based on two-dimensional photonic crystal

doi: 10.37188/CO.EN-2023-0014
Funds: Supported by Natural Science Foundation of Gansu Province (No. 21JR7RA289)
More Information
    Author Bio:

    WU Rong (1968—), female, born in Wuwei city, Gansu province, Professor, School of Electronic and Information Engineering, Lanzhou Jiaotong University. Her research interests are on semiconductor integrated circuit. E-mail: 759165367@qq.com

    ZHANG Hao-chen (1997—), male, born in Tongwei country, Gansu province, postgraduate, School of Electronic and Information Engineering, Lanzhou Jiaotong University. His research area centers primary on optical devices. E-mail: 2651809834@qq.com

    Corresponding author: 2651809834@qq.com
  • 摘要:

    在二维光子晶体中嵌入了线缺陷,利用线性干涉效应和波导耦合,设计了一种基于二维光子晶体的同或门和与非门结构。主要采用平面波展开法对该二维光子晶体的能带结构进行分析,采用时域有限差分法,结合线性干涉效应,在Rsoft平台对所设计的同或门和与非门进行稳定电场图和归一化功率仿真。仿真结果标明:设计的同或门对比度高达29.5 dB,响应时间为0.073 ps,数据传输速率为13.7 Tbit/s;设计的与非门对比度高达24.15 dB,响应时间为0.08 ps,数据传输速率为12.5 Tbit/s。这些结果表明所设计的结构对比度高、响应时间短和数据传输速率快。

     

  • Figure 1.  Energy band diagram of TE mode of photonic crystal

    Figure 2.  XOR gate structure

    Figure 3.  The steady-state electric field diagrams when the input is logic (a) '00', (b) '01', (c) '10' and (d) '11' respectively

    Figure 4.  The normalized power output curves when the input is logic (a) '00', (b) '01', (c) '10' and (d) '11' respectively

    Figure 5.  NAND gate structure

    Figure 6.  The stable electric field diagram and normalized power curve when the input logic is '00', '10' and '11', respectively. (a)-(c) are electric field diagrams when input logic is (a) '00', (b) '10', and (c) '11'; (d)-(f) are normalized curves when input logic is (d) '00', (e) '10', and (f) '00'

    Table  1.   Summarized features of proposed structure and previous works

    Works/yearsContrast ratio (dB)
    NANDNOR
    Ref. [17]/202019.44.6
    Ref. [18]/20225.75.9
    Ref. [19]/20235.97.7
    This work24.1529.5
    下载: 导出CSV
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出版历程
  • 收稿日期:  2023-07-28
  • 修回日期:  2023-08-07
  • 网络出版日期:  2023-09-22

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