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集成PIN光敏元的CMOS探测器光电响应特性研究

杨成财 鞠国豪 陈永平

杨成财, 鞠国豪, 陈永平. 集成PIN光敏元的CMOS探测器光电响应特性研究[J]. 中国光学(中英文), 2019, 12(5): 1076-1089. doi: 10.3788/CO.20191205.1076
引用本文: 杨成财, 鞠国豪, 陈永平. 集成PIN光敏元的CMOS探测器光电响应特性研究[J]. 中国光学(中英文), 2019, 12(5): 1076-1089. doi: 10.3788/CO.20191205.1076
YANG Cheng-cai, JU Guo-hao, CHEN Yong-ping. Study on the photo response of a CMOS sensor integrated with PIN photodiodes[J]. Chinese Optics, 2019, 12(5): 1076-1089. doi: 10.3788/CO.20191205.1076
Citation: YANG Cheng-cai, JU Guo-hao, CHEN Yong-ping. Study on the photo response of a CMOS sensor integrated with PIN photodiodes[J]. Chinese Optics, 2019, 12(5): 1076-1089. doi: 10.3788/CO.20191205.1076

集成PIN光敏元的CMOS探测器光电响应特性研究

详细信息
  • 中图分类号: TN2;O472+.8

Study on the photo response of a CMOS sensor integrated with PIN photodiodes

More Information
    Author Bio:

    YANG Cheng-cai (1992-):Tai'An, Shandong Province, Graduated from Northeastern University in 2016, and currently pursuing a master's degree in Shanghai Institute of Technical Physics, Chinese Academy of Sciences.He mainly engages in the research of CMOS image sensor design and read-out circuits design.E-mail:tomasyoung@mail.ustc.edu.cn

    CHEN Yong-ping (1963-):Professor, Shanghai Institute of Technical Physics, Chinese Academy of Sciences.His research interests are on design of high-performance CMOS image sensors.E-mail:chen_yp@mail.sitp.ac.cn

    Corresponding author: CHEN Yong-ping, E-mail:chen_yp@mail.sitp.ac.cn
  • 摘要: 传统的CMOS图像传感器一般采用基于LV-CMOS工艺的N阱/P型衬底制备的PN光电二极管或者PPD二极管作为光敏元。PIN光敏元具有结电容小、量子效率高的特点。采用HV-CMOS(高压CMOS)工艺可以实现CMOS电路与PIN光敏元的单片集成。本文研究了集成PIN光敏元的CMOS探测器的光电响应特性以及NEP随像素大小和复位电压的变化关系。研究表明,将光敏元从PN光电二极管改为PIN光电二极管后,像素电荷增益可以提高一个数量级左右;同时,像素的瞬态电荷增益要大于传统认为的1/Cpd,并与二极管的大小以及复位电压紧密相关。研究发现,小像素因其更高的电荷增益和更低的等效噪声,更加适合弱信号下的短积分时间快速探测。若配合微透镜的使用,小像素在微光探测方面可以获得更大的优势。

     

  • 图 1  HV-CMOS工艺示意图

    Figure 1.  Schematic diagram of HV-CMOS process

    图 2  PIN光敏元与CMOS电路单片集成

    Figure 2.  Monolithic integration of PIN photosensitive element and CMOS circuit

    图 3  HV-CMOS工艺中的3T像素结构

    Figure 3.  3T pixel structure in HV-CMOS process

    图 4  CMOS传感器读出电路

    Figure 4.  Read-out circuit in CMOS sensor

    图 5  PN和PIN空间电荷区

    Figure 5.  Space charge regions of PN and PIN

    图 6  结电容随偏压变化关系

    Figure 6.  Relationship between junction capacitance and bias voltage

    图 7  结电容与像素大小的关系

    Figure 7.  Relationship between junction capacitance and pixel size

    图 8  暗电流与偏置电压大小的关系

    Figure 8.  Relationship between dark current and bias voltage

    图 9  暗电流与尺寸L的变化关系

    Figure 9.  Relationship between dark current and pixel size

    图 10  结电压与光电流关系

    Figure 10.  Relationship between junction voltage and photo current

    图 11  光信号电压变化与光电流关系

    Figure 11.  Relationship between photo signal voltage variation and photo current

    图 12  瞬态电荷转换增益随光电流变化关系

    Figure 12.  Relationship between transient charge conversion gain and photo current variance

    图 13  瞬态电荷增益与电容值倒数的比较

    Figure 13.  Comparison between transient charge gain and the reciprocal of capacitance value

    图 14  CTIA结构示意图

    Figure 14.  Schematic diagram of a CTIA structure

    图 15  NEP与像素大小的关系

    Figure 15.  Relationship between NEP and pixel size

    表  1  公式参数

    Table  1.   Formula parameters

    Parameter PN photodiode(LV-CMOS) PIN photodiode(HV-CMOS)
    Area junction capacitance for zero bias:CJ 97 pF/mm2 0.93 pF/mm2
    Area capacitance grading coefficient:MJ 0.31 0.05
    Area capacitance junction potentials:PB 0.42 V 0.31 V
    Perimeter junction capacitance for zero bias:CJSW 0.52 pF/mm 0.35 pF/mm
    Perimeter capacitance grading coefficient:MJSW 0.21 0.21
    Perimeter capacitance junction potentials:PBSW 0.38 V 0.16 V
    Area leakage current density:JS 1.27 pA/mm2 2.07 pA/mm2
    Perimeter leakage current density:JSSW 28.8 fA/mm 2.91 pA/mm
    Voltage dependent area leakage conductivity:GLEAK 0 pA/V/mm2 0 pA/V/mm2
    Voltage dependent perimeter leakage conductivity:GLEAKSW 44 fA/V/mm 1.29 pA/V/mm
    下载: 导出CSV
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出版历程
  • 收稿日期:  2018-11-07
  • 修回日期:  2018-12-29
  • 刊出日期:  2019-10-01

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